This invention relates generally to memory devices and particularly to dynamic random memory device with multilevel memory cells. A multi-level cell DRAM can store more than two voltage levels in the memory and thus can store more than 1 bit per cell. Although store four voltage levels in memory cells can achieve more density efficiency, in practice store three-level voltage in memory cells is easier due to the noise margin problem in multi-level DRAM.
Suggested Classification: 365/149; 365/189; 365/168; 365/94
T. Furuyama et al (“Furuyama”) in an article titled “An Experimental Two Bit/Cell storage DRAM for Macro Cell or Memory on Logic Application”, IEEE J. Solid State Circuits, volume 24, number 2, page 388 to 393, April 1989 proposed one multilevel sense and restore method. In this scheme, four voltages stored in the memory and mapped to two bits, as shown in FIG. 1. For sense operation, cell charge share with bit line and bit line is split into three sub bit lines and then isolated from one another via switches. These three sub bit lines will be connected to three sense amplifier SA, SA compare three sub bit lines with three reference voltages and output corresponding 2 bit data. This method can read 2 bit data out at one time and fast, but the disadvantage of this scheme is also very obvious that it need three sense amplifiers, more switches and control circuit for sub bit line and a worst disadvantage is that it's susceptibility to sense errors with unstable globe reference voltage and small noise margin. And even this scheme is faster comparing to the following scheme, it still need more switching operations and decoding operations, these operation make this scheme still slower than most conventional DRAM.
U.S. Pat. No. 5,283,761 to Gillingham discloses the method and circuit to form two pairs of sub bit lines, with each pair having a sense amplifier, unlike the parallel sensing in the Furuyama scheme, the Gillingham scheme uses sequential sensing. In sequential sensing, the result of the first sense amplifier is used to generate the reference for the second sensing operation. An initial sensing operation compares the multi-level cell voltage to VDD/2 and if cell voltage above VDD/2 then the second sensing operation will compare cell voltage (after charge share with bit line) to a voltage reference of 5VDD/6. Conversely, if the first operation reveals cell voltage below VDD/2, the second operation will compare cell voltage with a voltage reference of VDD/6. The results of the two sensing operations produce 2 bit data. This scheme uses a local generation of reference voltage and therefore can reduce some noise from globe reference voltage use in Furayama. The disadvantage of this scheme is that it still use 2 sense amplifier and has lots of control and switches circuit for sub bit line concept, it also has the problem of much low noise margin compare to conventional DRAM because needs more reference voltage levels. Furthermore, the speed is even slower than Furuyama's scheme.
U.S. Pat. No. 6,556,469 to Birk et al. discloses the method to combine the benefits of Furayama's parallel sensing and Gillingham's using of local reference voltage. Nevertheless, this scheme is limited by the prior scheme's low noise margin problem of multi-level DRAM.
U.S. Pat. No. 6,654,280 to Blodgett discloses the method to decode a two bit, 3-level memory cell to a three bit, 2-level memory cell. The nine possible states of the two cells are mapped into eight data states representing three binary data bits, and one spare state. The ninth state, State 8, is a spare state. The spare state may be used as an erased or unwritten state, or as an error state (data is invalid). This scheme can achieve 66% (⅔) memory array efficiency. The disadvantage for this scheme is that it has to read out the data (0 or 1 or 2) before it can do the decoding. For multi-level memory it needs more time to read out the data than conventional 2-level memory since more operations are need to determine the stored voltage level. Therefore the memory sense speed of this method will be slower than the conventional 2-level DRAM.